🔍 Deep Dive: IC Designer's Corner News and Insights - EDN

EDN Staff October 12, 2026 0

AI silicon tapeout: Can it beat a benchmark engineers trust?

Can the engineering data prove the improvement in silicon design rather than relying on one successful run or thousands of tool Continue Reading...

C.H. Chien September 15, 2026 0

Design IC Designer's Corner

A design path to success exists for ultra-low-voltage SoCs

The alien realm of ultra-low voltage (ULV) in chip design means supply voltages near or below transistor threshold Continue Reading...

Dr. Moh Kolbehdari September 2, 2026 0

Design IC Designer's Corner

Why a nine-month AI chip tape-out matters

In AI-assisted chip design, parallelism creates speed and intelligence-aware control keeps the design Continue Reading...

John Elliott August 25, 2026 0

Design IC Designer's Corner

Hardware security verification must go beyond functional testing

Security verification must go beyond functional testing to assess whether security objectives are maintained across SoC Continue Reading...

Lauro Rizzatti August 11, 2026 0

Design IC Designer's Corner

Inference 2.0: How enterprise AI is reshaping AI system architectures

Enterprise AI is turning inference from a model-level computation into a context-aware workflow. System architects must now reconsider what AI performance really Continue Reading...

Lauro Rizzatti July 22, 2026 0

Design IC Designer's Corner

Enterprise AI: Reshaping AI processor architectures

Enterprise AI fundamentally changes the computing requirements, exposing the architectural limits of GPUs and opening the door for real-time, memory-centric, low-latency Continue Reading...

Jason Szu-Sheng Kang July 14, 2026 0

Design IC Designer's Corner

Crypto mining SoC unearths a need for custom IP

Here is how the impact of custom cells can ripple through the SoC design flow, from tape-out and Continue Reading...

Mia Chang July 7, 2026 0

Design IC Designer's Corner Uncategorized

Memory wall: Why cache miss tolerance defines CPU performance now

Here are six "memory wall" insights gained from evaluating the FlatBuffers workload on a RISC-V Continue Reading...

Nicky Khodadad, Nguyen Vu and Ashish Darbari June 30, 2026 1

Design IC Designer's Corner

Hidden underflow in BF16 divider in mixed-precision FP designs

Mixed-precision and transprecision floating-point designs offer compelling benefits but also amplify the risk of subtle correctness Continue Reading...

Rocco Jonack June 17, 2026 0

Design IC Designer's Corner

Model your IPs and your NoCs

Here is why abstraction levels matter and why the interconnect can’t be an afterthought in SoC Continue Reading...